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Bluetooth LE 5.3 transceiver integrating Controller and Host layers

• Supported data rates: 1 Mbps, 2 Mbps, and Long Range (500 kbps, 125 kbps)

• TX power: Up to 15 dBm

• RX sensitivity: –99 dBm @ 1 Mbps

• Radio consumption @ 3.3 V VBAT input:

  • 6.7 mA TX current @ 0 dBm output power (DC-DC supply, 64 MHz system clock)

  • 87 mA TX current @ 15 dBm output power (SYS_LDO supply, 64 MHz system clock)

  • 5.7 mA RX current @ 1 Mbps (DC-DC supply, 64 MHz system clock)

Arm^® Cortex^®-M4F 32-bit micro-processor with floating point support

• Up to 64 MHz clock frequency

• Built-in Memory Protection Unit (MPU) supporting eight programmable regions

• Hardware Floating Point Unit (FPU)

• Built-in Nested Vectored Interrupt Controller (NVIC)

• Non-maskable Interrupt (NMI) input

• Serial Wire Debug (SWD) with 16 breakpoints, two watchpoints, and a debug timestamp counter

On-chip memory

• ROM for chip bootloader, system drivers, and Bluetooth LE Protocol Stack code

• 96 KB RAM for data and instruction code, with retention capabilities in sleep mode

• 512 KB Flash for code, system parameter configuration, and user data

Digital peripheral

• One general-purpose DMA engine with five channels and up to 16 programmable request/trigger sources

Analog peripherals

• One 13-bit Sense ADC with a sampling rate of 1 Msps, supporting up to five external I/O channels and three internal signal channels

• Built-in die temperature and voltage sensors

• Low-power comparator, supporting wakeup from sleep mode

Flexible serial peripherals

• Two UART modules up to 2 Mbps with flow control and IrDA features

• Two I2C modules for peripheral communication, up to 1 MHz

• One SPI master interface and one SPI slave interface for host communication

Security

• Complete secure computing engine

  • AES 128-bit security module (ECB, CBC)

  • True random number generator (TRNG)

I/O peripherals

• 24 multiplexed I/O pins in total

  • Nine general-purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors

  • Eight always-on I/O (AON I/O) pins, supporting wakeup from sleep mode

  • Seven mixed signal I/O (MSIO) pins, configurable to be digital/analog signal interfaces

Timers

• Two general-purpose, 32-bit timer modules

• One dual timer module composed of two programmable 32-bit or 16-bit down counters

• One sleep timer for waking the device up from sleep mode

• Two 3-channel PWM modules with edge alignment mode and center alignment mode

• One real-time counter (RTC)

Power management

• On-chip DC-DC/SYS_LDO to provide RF analog voltage and supply CORE_LDO

• Supply voltage: 2.3 V – 3.6 V

Low-power consumption

• Sleep mode: 3.3 µA (Typical) at 3.3 V VBAT input, with 48 KB SRAM retention on, wakeup sources from AON I/Os, and LFXO_32K running

• Ultra deep sleep mode: 2.6 µA (Typical), with no memory data in retention and wakeup sources from SLP Timer or AON I/Os

• OFF mode: 200 nA (Typical), with system in reset mode

Package

• Wettable flank-plated QFN40: 6.0 mm * 6.0 mm * 0.75 mm, 0.5 mm pitch

Operating temperature range

• –40°C to 105°C